AMD outlines its quad-core computing

The native quad-core designs will share the existing Socket F architecture and thermal envelope

Alun Williams
19 Sep 2006

Page 1 of 2 AMD outlines its quad-core computing

AMD has been revealing details of its technology roadmap, specifically what lies ahead with quad-core computing.

Scheduled to appear in the first half of 2007 - first for servers, but then rolled out across AMD desktop and laptop offerings - this will be the next step for AMD multi-core processing.

AMD's Technical Director, Sales & Marketing EMEA, Giuseppe Amato, outlined details of the 65nm process-based quad-cores that we can expect. These include 2MB of a new Level 3 cache, which is shared by all the cores on the die, as well as 512KB of Level 2 cache and 64KB of Level 1 cache, which is most tightly integrated with the processors.

The native design - the four cores will share the same silicon substrate - will also be compatible with the existing Socket F (1207) and share the same (95W) thermal envelope. What this means, Amato pointed out, will be an easy route for organisations to scale up performance, without worrying about the image management implicit in migrating along Intel's processors, for example from single core Xeons to multi-core Xeons to Itaniums.

The main elements he highlighted were the 65nm SOI (Silicon-on-Insulator) process technology (with AMD fine-tuning transistor characteristics to minimise power leakage), improved Power Now! management (which saves power depending on how idle the individual cores are operating), an integrated memory controller (which can operate at the processor's clock-speed, reducing memory latency by avoiding the bottlenecks of external operation) and the Direct Connect Architecture (providing faster CPU-to-CPU operation and improved I/O throughput).

He was, he insisted, speaking from a position of strength, as he highlighted AMD's capture of 25.9 per cent of the x86 server market in Q2 of 2006 (a 130 per cent year-on-year gain), which was achieved 'in spite of the anti-competitive behaviour of Intel.'

The real agenda for the briefing, of course, was to highlight AMD's progress ahead of next week's Intel Developer Forum Fall 2006, when Intel is expected to announce its own form of 'quad' computing.

Among the many Intel digs, he said that Intel may rush a 'dual die' architecture (two separate dual-cores packaged together) to market in order to claim 'first to market, only to change the design to true quad-core later, resulting - he claimed - in more churn and increased total cost of ownership for customers.

Getting more technical, AMD quad-core details listed include: 32-bit instruction fetch, enhanced branch prediction, out-of-order load execution, dual 128-bit SSE dataflow (up from 64-bit), up to four dual precision floating point ops/cycle (up from 2 ops/cycle), dual 128-bit loads per cycle, Bit Manipulation extensions (LZCNT/POPCNT) and SSE extensions (EXTRQ/INSERTQ, MOVNTSD/MOVNTSS).

Beyond the CPU itself, there will be 8GB/sec HyperTransport links (via Hyper Transport 3.0), an enhanced crossbar design and DDR2 support. This can be achieved, he said, by the bus controllers running at processor speeds, courtesy of the integrated architecture.

The main AMD message, however, was the increasing benefits of its Direct Connect Architecture. AMD's approach to reducing the traditional x86 architecture front side bus bottlenecks means it can side-step the scalability problems that it claims Intel faces, he believes. In other words, the more cores that are involved in communications, the more efficient their integration has to be and the more direct their communications have to be. Otherwise, adding more 'engines' may negatively effect performance. Thus, Amato claims, Intel will be stepping backwards with regards to the throughput for its Clovertown cores, compared to current Woodcrest offerings.

Page 1 of 2 AMD outlines its quad-core computing

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