Intel Xeon 5500 series review

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After much speculation and anticipation, Intel’s new 5500 Series Xeon processors have finally arrived – and judging by the number of new features and improvements on offer the wait looks well worthwhile.

Codenamed “Nehalem”, Intel’s new micro-architecture represents the next step in its ‘tick-tock’ design model where the last phase was to introduce the Core architecture and then shrink it to 45nm.

Nehalem delivers the next ‘tock’ phase but it’s far more significant than that as it represents a sea change in processor design. Instead of presenting a one-size-fits-all solution, Nehalem effectively offers a set of building blocks. This allows it to scale not only across different hardware but also across different market sectors, including mobile, desktop and server DP and MP applications.

We’ve already covered Intel’s Core i7 implementation and now we look closer at the 5500 series “Gainestown” Xeon DP server processors.

Tech specs

The new processors still use the 45nm manufacturing process but the four cores are on a single die and all share one chunk of L3 cache, which can be up to 8MB. They use the same L1 cache as the existing Core technology but have a lower latency 256KB L2 cache per core.

The processors use a larger LGA1366 socket and the main reason for the increase in size is the processors now incorporate an integrated memory controller and a link controller for Intel’s new QPI (Quick Path Interconnect).

You can wave goodbye to the trusty old FSB which was used to create a backbone between the processors and the chipset’s memory controllers and I/O bus. It worked well enough but created a bottleneck as all system memory was in a single, shared location.

The QPI facilitates high-speed connections between processor and I/O controller. Each processor has its own dedicated memory which it accesses via its integrated controller. It uses the QPI for fast access to the I/O controller and the 5500 series Xeons also have a QPI link between dual-processor sockets.

The first generation Bloomfield processor launched in 2008 is designed for single socket desktops and does not have the QPI links needed to communicate with a second processor.

The QPI operates at speeds of up to 25.6GB/sec or 6.4GT/sec (GigaTransfers/data transfers/operations per second).

It effectively allows all system memory to be no more than one hop away from any processor and as QPI is point-to-point there is none of the single bus contention in the FSB. If one processor needs to access the memory on the other processor it can do so via QPI links.

Intel’s Turbo Boost technology uses the fact that most apps don’t scale to an arbitary number of CPUs. A controller on the processor monitors the load and can power down a core if it isn’t being used. This creates thermal/power headroom which can be passed on to the other cores and used to boost their speed.

The more cores that are powered down the more boost is available to the active cores and frequencies are raised in bins, or 133MHz increments. For example, a 2.8GHz X5560 Xeon could be boosted to 3GHz with three or four active cores and up to 3.2GHz with one or two cores active.

As FSB leaves the building Intel now reacquaints us with HyperThreading which allowed older Pentium and Xeon processors to simultaneously run two threads per core. For Nehalem, this hasn’t changed in principle but the larger cache and higher bandwidth means that, dependent on the application, it can realise a significant performance improvement for fully multithreaded apps.

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