IBM shows off working “racetrack” memory
IBM claims it has turned a trio of promising technologies into working prototypes made using real-world manufacturing techniques.
According to IBM, the achievements in different fields mark a potentially pivotal step in solving several issues in the tech world, such as the long discussed end of the road for Moore’s Law.
“Following years of key physics advances previously only achieved in a laboratory, IBM scientists successfully integrated the development and application of new materials and logic architectures on 200mm diameter wafers,” the company said.
“These breakthroughs could potentially provide a new technological basis for the convergence of computing, communication, and consumer electronics.”
The company said that with almost all current electronic equipment built on complementary-symmetry metal–oxide–semiconductor (CMOS) technology, industry needed new materials and circuit architecture designs that were compatible with existing engineering processes.
These breakthroughs could potentially provide a new technological basis for the convergence of computing, communication, and consumer electronics
“Racetrack memory” is touted by IBM as combining the strengths of magnetic drives and solid state memory, and could solve the problem of marrying growing data storage requirements with smaller devices.
The company said it had produced the first racetrack memory device integrated with CMOS technology on 200mm wafers.
The researchers demonstrated both read and write actions on an array of 256 magnetised horizontal racetracks and claimed the breakthrough could lead to “a new type of data-centric computing that allows massive amounts of stored information to be accessed in less than a billionth of a second”.
Graphene on show
IBM also said it had made the first ever CMOS compatible graphene device, which would improve wireless communication in intemperate environments.
According to the company, the graphene frequency multiplier works up to 5GHz and in temperatures of 200 degrees, but it relied on a new architecture that turned existing graphene transistor manufacturing on its head.
Instead of trying to add gates to an inert graphene surface, the researchers used an embedded gate structure that they said enabled good yields from a 200mm wafer.
Rounding off the triple announcement, IBM also demonstrated the first transistor with sub-10nm channel lengths, which should outperform silicon-based devices at such tiny scales.
IBM said the nanotube technology would supersede conventional silicon technology, which “will have extreme difficulty performing even with new advanced device architectures”.