Sony, IBM raise the curtain on nine core Cell processor
At the International Solid State Circuits Conference, Sony and IBM and finally gave details of the much hyped ‘Cell’ processor.
Although popularly understood to be the processor which will power the forthcoming Playstation 3 games console from Sony, it is clear that the partners intend the processor to become the heart of a wide range of applications from imbedded devices right through to servers.
The prototype measures 221mm square, built on a 90 nanometer processor and integrates 234 million transistors. The partners say that current versions of the device run up to 4GHz.
The real revolution is in the number of cores in the chip. The basic design consists of one 64-bit PowerPC processor core and eight separate processing cores. These are being referred to as ‘synergistic processing elements’, or SPEs. Using techniques borrowed from IBM’s mainframes known as virtualisation, the cores can support multiple operating systems and programming models.
Multicore have become this year’s must have feature for new processors. As chip designers have come up against problems of overheating and the laws of quantum mechanics, they have been forced to turn away from traditional single core designs and move towards a multicore future. Whilst AMD already has dual core offerings and Intel is promising dual core Pentiums in the future, neither of them have anything quite like the Cell.
The group says that Cell can support multiple operating systems – including Linux, real time operating systems of the kind found in games consoles like the Playstation as well as guest OSs for specific applications simultaneously. IBM, Sony and Toshiba are said to be already speaking to open source programmers to develop a set of development tools for the Cell. This is bound to re-ignite the rumours that the underlying Playstation 3 operating system will be some form of Linux.
The dual-threaded PowerPC operates as the control processor for the eight single-threaded SPEs. The SPEs are optimised for floating-point calculations, which are vital for everything from real time graphics simulations on games consoles right through to supercomputer applications like weather forecasting.
The PowerPC core is supplied with 32Kb of Level 1 cache and 512Kb of Level 2 cache whilst the SPEs have 256Kb of cache memory apiece.
The cores have a shared bus that moves data into and out of the SPEs, Suzuoki says. Data is transferred via memory and I/O controllers that are integrated into the chip itself rather than needing a separate chip set. These interfaces were designed by RAMBus and uses the company’s XDR (eXtreme Data Rate) technology running at 3.2GHz for the memory and FlexIO running at 6.4GHz for the I/O on the prototype.
The first commercial appearance of the Cell is likely to be the Playstation 3 next year by which point production may well be on a 65nm process. It is more than likely that Apple will be looking hard at the chip for a new generation of Macs. IBM is likely to be pushing the Cell hard as the basis for future servers and workstations.
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